The present invention relates to a disk array device, a disk array system and a cache control method.
Disk array devices frequently employ a duplicate (redundant) internal configuration for the purpose of improving disaster tolerance. The duplication of controllers as in the disk array device shown in FIG. 1 or the storage device controller indicated in Japanese Patent Application Laid-open No. 2005-115603 is an example of duplicating a disk array device. As a result of employing such a configuration, even if a failure should occur in a prescribed portion of the disk array device, the disk array device is able to continue to operate and enable prompt repair.
A disk array system 100 shown in FIG. 1 has a configuration in which a disk array device 2′ is connected with a host device 1 via a network, and the disk array 2′ has duplicate controllers 3′M and 3′S therein. Each of the controllers 3′M and 3′S respectively has cache memories 5′M and 5′S for temporarily storing data, and employs a functional configuration respectively having I/O transmission/reception units 4′M and 4′S for transmitting and receiving data and the like to and from the host device 1, and cache memory control units 7′M and 7′S for controlling input and output of data in the cache memories 5′M and 5′S.
In this disk array system 100, write requests cannot be simultaneously transmitted to the cache memory control unit 7′M of the master controller 3′M and the cache memory control unit 7′S of the slave controller 3′S. This is because if write requests are transmitted simultaneously, both write requests end up crossing between the controllers 3′M and 3′S, resulting in different data being stored in their respective cache memories 5′M and 5′S. Consequently, there is a high possibility of the occurrence of data mismatch between the cache memories 5′M and 5′S, resulting in an increased likelihood of loss of data consistency.
Therefore, in this conventional disk array system 100, in the case of designating one of the controllers as the master controller 3′M having master authority for controlling the other controller and designating the other controller as the slave controller 3′S, the procedure by which write data is written to the cache memories 5′M and 5′S is carried out in the manner described below in order to maintain consistency of write data transmitted from the host device 1.
First, in the case the I/O transmission/reception unit 4′M of the master controller 3′M has received a write request from the host device 1 (S1), the I/O transmission/reception unit 4′M of the master controller 3′M determines that its own controller has master authority and transmits the write request to the cache control unit 7′M of the master controller 3′M (S2). When the cache control unit 7′M of the master controller 3′M receives the write request, the cache control unit 7′M of the master controller 3′M stores write data transmitted from the host device 1 following the write request to the cache memory 5′M via the I/O transmission/reception unit 4′M of the master controller 3′M (S3).
Subsequently, the cache control unit 7′M of the master controller 3′M transmits the write request to the cache control unit 7′S of the slave controller 3′S (S4), and transmits write data stored in the cache memory 5′M of the master controller 3′M to the cache memory 5′S of the slave controller 3′S (S5). When the cache control unit 7′S of the slave controller 3′S stores write data in the cache memory 5′S, a write data storage completion report is transmitted to the cache control unit 7′M of the master controller 3′M (S6). The cache control unit 7′M of the master controller 3′M transmits the storage completion report to the I/O transmission/reception unit 4′M of the master controller 3′M (S7), and the I/O transmission/reception unit 4′M of the master controller 3′M transmits the storage completion report to the host device 1 (S8).
On the other hand, in the case the I/O transmission/reception unit 4′S of the slave controller 3′S has received a write request from the host device 1, write data is written to the cache memories 5′M and 5′S as shown in FIG. 2.
First, in the case the I/O transmission/reception unit 4′S of the slave controller 3′S has received a write request from the host device 1 (S11), if the I/O transmission/reception unit 4′S of the slave controller 3′S determines that its own controller does not have master authority, the I/O transmission/reception unit 4′S of the slave controller 3′S transmits the write request to the cache control unit 7′M of the master controller 3′M (S12). In addition, if the I/O transmission/reception unit 4′S of the slave controller 3′S receives write data from the host 1, the I/O transmission/reception unit 4′S of the slave controller 3′S transmits the received write data to the cache control unit 7′M of the master controller 3′M.
When the cache control unit 7′M of the master controller 3′M receives the write request, the cache control unit 7′M of the master controller 3′M stores write data transmitted following the write request to the cache memory 5′M (S13). Subsequently, the cache control unit 7′M of the master controller 3′M transmits the write request to the cache control unit 7′S of the slave controller 3′S (S14), and transmits the write data stored in the cache memory 5′M of the master controller 3′M to the cache memory 5′S of the slave controller 3′S (S15).
When the cache control unit 7′S of the slave controller 3′S stores the write data in the cache memory 5′S, the cache control unit 7′S of the slave controller 3′S transmits a write data storage completion report to the cache control unit 7′M of the master controller 3′M (S16). The cache control unit 7′M of the master controller 3′M transmits the storage completion report to the I/O transmission/reception unit 4′S of the slave controller 3′S (S17), and the I/O transmission/reception unit 4′S of the slave controller 3′S transmits the storage completion report to the host device 1 (S18).
In this manner, in the case the slave controller not having master authority has received a write request during execution of write processing in a disk array device, the slave controller must again receive a write request and write data from a master controller after having already transmitted the write request and write data to the master controller, thereby resulting in unnecessary data transfer.
In addition, in the case of a disk array system in which duplicate controllers are provided with a common cache memory, although the problem of unnecessary data transfer as described above does not occur, it is necessary to maintain consistency of write data by carrying out duplicate writing after each controller has carried out locking (exclusive control) on different storage areas within the cache memory. Since this locking processing requires time, as a result thereof, a large amount of time is required for writing processing thereby causing a decrease in response performance.